NXP Semiconductors /MIMXRT1021 /USDHC1 /SYS_CTRL

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Interpret as SYS_CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DVS_0)DVS0SDCLKFS0 (DTOCV_0)DTOCV0 (IPP_RST_N)IPP_RST_N 0 (RSTA_0)RSTA 0 (RSTC_0)RSTC 0 (RSTD_0)RSTD 0 (INITA)INITA 0 (RSTT)RSTT

RSTD=RSTD_0, RSTA=RSTA_0, RSTC=RSTC_0, DTOCV=DTOCV_0, DVS=DVS_0

Description

System Control

Fields

DVS

Divisor

0 (DVS_0): Divide-by-1

1 (DVS_1): Divide-by-2

14 (DVS_14): Divide-by-15

15 (DVS_15): Divide-by-16

SDCLKFS

SDCLK frequency select

DTOCV

Data timeout counter value

0 (DTOCV_0): SDCLK x 2 14

1 (DTOCV_1): SDCLK x 2 15

2 (DTOCV_2): SDCLK x 2 16

3 (DTOCV_3): SDCLK x 2 17

4 (DTOCV_4): SDCLK x 2 18

5 (DTOCV_5): SDCLK x 2 19

6 (DTOCV_6): SDCLK x 2 20

7 (DTOCV_7): SDCLK x 2 21

8 (DTOCV_8): SDCLK x 2 22

9 (DTOCV_9): SDCLK x 2 23

10 (DTOCV_10): SDCLK x 2 24

11 (DTOCV_11): SDCLK x 2 25

12 (DTOCV_12): SDCLK x 2 26

13 (DTOCV_13): SDCLK x 2 27

14 (DTOCV_14): SDCLK x 2 28

15 (DTOCV_15): SDCLK x 2 29

IPP_RST_N

Hardware reset

RSTA

Software reset for all

0 (RSTA_0): No reset

1 (RSTA_1): Reset

RSTC

Software reset for CMD line

0 (RSTC_0): No reset

1 (RSTC_1): Reset

RSTD

Software reset for data line

0 (RSTD_0): No reset

1 (RSTD_1): Reset

INITA

Initialization active

RSTT

Reset tuning

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